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1/16 ? semiconductor msm512805c description the msm512805c is a 262,144-word 8-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the msm512805c achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/single-layer metal cmos process. the msm512805c is available in a 26/24-pin plastic soj or 26/24-pin plastic tsop. features ? 262,144-word 8-bit configuration ? single 5 v power supply, 5% tolerance ? input : ttl compatible, low input capacitance ? output : ttl compatible, 3-state ? refresh : 512 cycles/8 ms ? fast page mode with edo, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? package options: 26/24-pin 300 mil plastic soj (soj26/24-p-300-1.27) (product : MSM512805C-XXJS) 26/24-pin 300 mil plastic tsop (tsopii26/24-p-300-1.27-k) (product : msm512805c-xxts-k) xx indicates speed rank. product family ? semiconductor msm512805c 262,144-word 8-bit dynamic ram : fast page mode type with edo msm512805c-50 50 ns 100 ns 80 ns 630 mw 735 mw family access time (max.) cycle time (min.) standby (max.) power dissipation msm512805c-40 t rac 40 ns 26 ns t aa 20 ns 14 ns t cac 10 ns 14 ns t oea 10 ns msm512805c-45 45 ns 90 ns 682.5 mw 24 ns 14 ns 14 ns operating (max.) 5.25 mw e2g0021-17-41 this version: jan. 1998 previous version: may 1997
2/16 ? semiconductor msm512805c pin configuration (top view) 3 4 5 9 10 11 12 13 24 23 22 18 17 16 15 14 2 25 1 26 26/24-pin plastic tsop (k type) 21 19 6 8 dq2 dq3 dq4 a0 a1 a2 a3 v cc dq1 v ss we ras dq7 dq6 dq5 a8 a7 a6 a5 a4 dq8 v ss cas oe 3 4 5 9 10 11 12 13 dq2 dq3 dq4 a0 a1 a2 a3 v cc 24 23 22 18 17 16 15 14 dq7 dq6 dq5 a8 a7 a6 a5 a4 2 dq1 25 dq8 1 v ss 26 v ss 26/24-pin plastic soj 6 we 21 cas 8 ras 19 oe pin name function a0 - a8 address input ras row address strobe cas column address strobe dq1 - dq8 data input/data output oe output enable we write enable v cc power supply (5 v) v ss ground (0 v) note: the same gnd voltage level must be provided to every v ss pin.
3/16 ? semiconductor msm512805c block diagram timing generator ras cas timing generator column address buffers internal address counter row address buffers a0 - a8 v cc v ss on chip v bb generator row de- coders word drivers memory cells refresh control clock sense amplifiers column decoders write clock generator i/o selector output buffers we oe 8 dq1 - dq8 8 8 8 8 8 input buffers 8 9 9 9 9
4/16 ? semiconductor msm512805c electrical characteristics absolute maximum ratings recommended operating conditions capacitance *: ta = 25 c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t symbol i os p d * t opr t stg C1.0 to 7.0 50 1 0 to 70 C55 to 150 rating ma w c c parameter v unit power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 5.0 0 typ. parameter 4.75 0 2.4 C1.0 min. 5.25 0 6.5 0.8 max. (ta = 0c to 70c) v unit v v v input capacitance (a0 - a8) input capacitance ( ras , cas , we , oe ) output capacitance (dq1 - dq8) c in1 symbol c in2 c i/o 6 7 7 max. pf unit pf pf parameter (v cc = 5 v 5%, ta = 25c, f = 1 mhz) typ.
5/16 ? semiconductor msm512805c dc characteristics parameter symbol condition msm512805 c-45 msm512805 c-50 msm512805 c-40 (v cc = 5 v 5%, ta = 0c to 70c) i oh = C5.0 ma output high voltage i ol = 4.2 ma output low voltage 0 v v i 6.5 v; all other pins not input leakage current under test = 0 v dq disable output leakage current 0 v v o 5.25 v ras , cas cycling, average power t rc = min. supply current (operating) ras , cas = v ih power supply ras , cas current (standby) ras cycling, average power cas = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cas = v il , current (standby) dq = enable average power cas before ras supply current ( cas before ras refresh) ras = v il , average power cas cycling, supply current t hpc = min. (fast page mode) v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i cc7 3 v cc C0.2 v min. 2.4 0 C10 C10 max. v cc 0.4 10 10 130 2 1 130 5 130 100 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 120 2 1 120 5 120 90 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 140 2 1 140 5 140 110 unit v v m a m a ma ma ma ma ma ma note 1, 2 1 1, 2 1 1, 2 1, 3 ras cycling, notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih .
6/16 ? semiconductor msm512805c ac characteristics (1/2) random read or write cycle time read modify write cycle time fast page mode cycle time fast page mode read modify write cycle time access time from ras access time from cas access time from column address access time from cas precharge cas to data output buffer turn-off delay time transition time ras precharge time ras pulse width ras pulse width (fast page mode with edo) ras hold time cas pulse width cas hold time ras to cas delay time ras to column address delay time cas to ras precharge time row address set-up time row address hold time column address set-up time column address hold time column address hold time from ras column address to ras lead time access time from oe oe to data output buffer turn-off delay time refresh period ras hold time referenced to oe ras hold time from cas precharge t rc t rwc t hpc t rac t cac t aa t cpa t cez t t t rp t ras t rasp t rsh t cas t csh t rcd t rad t crp t asr t rah t asc t cah t ral t oea t oez t ref t roh t rhcp output low impedance time from cas t clz cas precharge time (fast page mode with edo) t cp data output hold after cas low we to data output buffer turn-off delay time ras to data output buffer turn-off delay time t doh t wez t rez oe hold time from cas (dq disable) ras to second cas delay time t cho t rscd parameter msm512805 c-45 msm512805 c-50 msm512805 c-40 (v cc = 5 v 5%, ta = 0c to 70c, input pulse levels 0 v to 3 v) note 1, 2, 3 unit symbol t hprwc t ar note 4, 5, 6 4, 5 4, 6 4 7, 8 5 6 4 7 4 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns 7, 8 ns 7 ns ns ns min. 80 130 20 70 0 0 2 30 40 40 10 10 10 40 15 10 5 0 5 0 10 30 20 0 10 25 5 0 0 5 40 max. 40 10 20 25 12 50 10,000 100,000 10,000 30 20 10 12 8 12 12 min. 100 150 20 77 0 0 2 40 50 50 14 10 10 50 18 13 5 0 8 0 13 40 26 0 10 30 5 0 0 5 50 max. 50 14 26 30 12 50 10,000 100,000 10,000 36 24 14 13 8 12 13 min. 90 140 20 75 0 0 2 35 45 45 14 10 10 45 17 12 5 0 7 0 12 35 24 0 10 5 0 0 5 45 28 max. 45 14 24 28 12 50 10,000 100,000 10,000 31 21 14 12 8 12 12
7/16 ? semiconductor msm512805c ac characteristics (2/2) write command pulse width write command to cas lead time write command to ras lead time data-in set-up time data-in hold time from ras cas to we delay time ras to we delay time column address to we delay time ras to cas hold time ( cas before ras ) cas active delay time from ras precharge data-in hold time write command hold time write command hold time from ras oe command hold time oe to data-in delay time write command set-up time ras to cas set-up time ( cas before ras ) cas precharge we delay time read command set-up time read command hold time read command hold time referenced to ras oe precharge time we pulse width (dq disable) oe command hold time msm512805 c-45 msm512805 c-50 msm512805 c-40 (v cc = 5 v 5%, ta = 0c to 70c, input pulse levels 0 v to 3 v) note 1, 2, 3 t wp t cwl t rwl t ds t dhr t cwd t rwd t awd t csr t chr t rpc t dh t wch t wcr t wpe t oed t wcs parameter symbol unit note t rcs t rch t rrh t oeh t och t oep t cpwd 11 10 10 10 11 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 max. ns ns ns min. 10 10 10 0 30 30 60 40 10 20 0 10 10 30 10 10 0 45 5 7 7 0 0 0 max. min. 10 14 14 0 40 38 75 52 10 25 0 13 13 40 13 13 0 5 7 7 50 0 0 0 max. min. 10 14 14 0 35 36 70 48 10 25 0 12 12 35 12 12 0 46 5 7 7 0 0 0
8/16 ? semiconductor msm512805c notes: 1. a start-up delay of 200 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 2 ttl loads and 50 pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t cez (max.), t rez (max.), t wez (max.) and t oez (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. t cez and t rez must be satisfied for open circuit condition. 9. t rch or t rrh must be satisfied for a read cycle. 10. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. these parameters are referenced to the cas leading edge in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle.
9/16 ? semiconductor msm512805c timing waveform read cycle write cycle (early write) "h" or "l" ras cas v ih v il C C v ih v il C C dq v oh v ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t aa t roh t oea t cac t rac t oez t cez open t clz valid data-out t rez "h" or "l" ras cas v ih v il C C v ih v il C C dq v ih v il C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t rcd t csh t rsh t crp t cas t rad t rah t asr t asc t cah row column t wcs t wch t wcr t dhr t ds t dh valid data-in t wp t ral open t rwl t cwl e2g0095-17-41h
10/16 ? semiconductor msm512805c read modify write cycle "h" or "l" ras cas v ih v il C C v ih v il C C dq v i/oh v i/ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rwc t ras t rp t ar t crp t csh t rcd t crp t rsh t cas t asr t rah t asc t cah row column t cwd t cwl t rwd t rwl t wp t aa t awd t oea t oed t cac t rac t oez t ds t dh t clz valid data-out valid data-in t rad t rcs t oeh
11/16 ? semiconductor msm512805c fast page mode read cycle (part-1) fast page mode read cycle (part-2) C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cah t asc t rad t rcs t aa t rrh t ar t cac t clz t cpa t oea valid data-out valid* data-out t rah t asr t cah t asc t cah t asc t rac valid data-out t aa t cac t doh valid* data-out t cac t rez t oez t oez t cho t och t aa t oea t oep t oep t oea * : same data, t rscd t cp t rhcp e e e e e e e e v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cp t cah t asc t rad t rcs t rch t rac t aa t ar t cac t clz t wez t oea valid data-out valid data-out valid data-out t rah t asr t cah t asc t cah t asc t cac t aa t doh t cez t cpa t aa t cac t rcs t wpe t rscd t rhcp
12/16 ? semiconductor msm512805c fast page mode write cycle (early write) fast page mode read modify write cycle C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v i/oh v i/ol t asr row column t rasp t cwd t rah column t rcd t cp t asc t cah t cpa t asc t rad t rwd "h" or "l" valid data-out t oez t oed t ds t wp t awd t rcs t cwd t rwl t cac t awd t rac t wp t clz t dh t oeh valid data-in t oea valid data-out t oez t oed t cac t dh t oeh valid data-in t oea t clz t ds t aa t aa t rcs t cah t cpwd t hprwc t crp t ar t cwl t rscd e e e e e e e e v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v ih v il t asr row column t crp t rp t rasp t cas t csh t rah column column t rcd t cp t cas t cas t hpc t cp t hpc t asc t cah t cah t cah t asc t asc t rad t ar "h" or "l" t dh t ds t wch valid data-in t ds t dh t ds t dh t wch t wch t rsh valid data-in valid data-in t dhr t wcs t wcs t wcs t rscd
13/16 ? semiconductor msm512805c ras -only refresh cycle cas before ras refresh cycle ras cas v ih v il C C v ih v il C C address v ih v il C C t rc t ras t rp t crp t rpc t asr t rah row "h" or "l" dq v oh v ol e e note: we , oe = "h" or "l" t cez open ras cas v ih v il C C v ih v il C C t chr note: we , oe , address = "h" or "l" dq v oh v ol C C t rc t rp t ras t rp t rpc t cp t csr t rpc t cez open
14/16 ? semiconductor msm512805c hidden refresh read cycle hidden refresh write cycle C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v ih v il "h" or "l" t asr row column t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ral t rwl t chr t ras t rc t rp t ar t dhr t ds t wp t wch t dh valid data-in t wcr t wcs ras cas address oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C "h" or "l" we v ih v il C C dq v oh v ol C C t rc t rc t ras t rp t ras t rp t ar t crp t rcd t rsh t chr t rad t asr t rah t asc t cah row column t rcs t ral t rrh t aa t roh t oea t cac t rac t clz t oez valid data-out open t cez t rez
15/16 ? semiconductor msm512805c (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj26/24-p-300-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.80 typ. mirror finish
16/16 ? semiconductor msm512805c (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.29 typ. tsop ii 26/24-p-300-1.27-k mirror finish

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